95 www.ptcc.com.tw as23xx secondary side housekeeping circuit semiconductor features standard pc power good: uv detection on 4 rails uv detection of ac/bulk supply ov detection on 4 rails open collector pg out programmable fault output: ov ov plus uv ov plus uv after start-up delay ov crow-bar driver digital on/off input 2.5 v voltage reference operates from 5 v or 12 v rail pin configuration top view description the as23xx is a housekeeping circuit for monitoring the outputs of power supplies. it directly senses all the output rails without the need for exter- nal dividers and detects undervoltage and overvoltage. it also provides an additional undervoltage comparator which may be configured with any arbitrary hysteresis to sense a divided down representation of the ac bulk voltage. the housekeeping section provides all the features necessary to allow external caps to set the common timing features of pc type power supplies. in addition, negative rails may be sensed without the necessity of a v ee connection, and negative sensing may be disabled without affecting operation of the positive sense section. the 2.5 v series refer- ence is available and can source up to 5 ma. this ic is available in 16 lead packages. outputs include a pok (power ok) and a fault signal. the AS2333 includes sensing for 12 v, 5 v, and 3.3 v. the as2350 exchanges a ? v sense capability for the 3.3 v input. the as2316 mon- itors all supply voltages, but lacks cbd (crow-bar driver). as2350 pdip fault v ref uvb delay v cc +12v +5v ?v pok pgcap ac ?2v gnd hyst off as2350 soic fault v ref uvb delay v cc +12v +5v +3.3v pok pgcap ac ?2v gnd hyst off AS2333 pdip fault v ref uvb delay v cc +12v +5v +3.3v pok pgcap ac ?2v gnd hyst gnd AS2333 soic fault cbd cbd cbd cbd v ref uvb delay v cc +12v +5v +3.3v pok pgcap ac ?2v gnd hyst off as2316 pdip fault v ref uvb delay v cc +12v +5v +3.3v pok pgcap ac ?v ?2v gnd 1 2 3 4 16 15 14 13 5 6 7 12 11 10 off hyst 89 as2316 soic fault v ref uvb delay v cc +12v +5v +3.3v pok pgcap ac ?v ?2v gnd 1 2 3 4 16 15 14 13 5 6 7 12 11 10 off hyst 89 1 2 3 4 16 15 14 13 5 6 7 12 11 10 89 1 2 3 4 16 15 14 13 5 6 7 12 11 10 89 1 2 3 4 16 15 14 13 5 6 7 12 11 10 89 1 2 3 4 16 15 14 13 5 6 7 12 11 10 89 ordering information model sense voltage crow-bar driver as2316d, as2316n 12/ 5/+3.3 no AS2333d, AS2333n 12/+5/+3.3 yes as2350d, as2350n 12/ 5 yes
96 www.ptcc.com.tw as23xx secondary side housekeeping circuit functional block diagram + uv + disable + + 12v ac hyst off + v cc v ref v ref v cc v cc v cc v cc v ref v ref v ref v ref 2.5v v ref v cc v cc hyst npok nuv v ref v ref nreset nac warning noff warning + ov + uv + disable + + + ov + ov nov nov nuv nov latch nuv latch nfault nreset nuv latch nreset nuv nov + uv + ov + ov + uv + uv 5v +3.3v +5v +12v t t 20 s delay latch r sq latch r sq fault latch r s q 500 cbd cbd latch powers up in reset state + v cc uvb pgcap 1 a 20 s delay v cc 1 a 1 a pok delay nfault + chip bias v cc gnd
97 www.ptcc.com.tw as23xx secondary side housekeeping circuit pin function description (for AS2333/as2350) pin number function description 1v cc power input to the chip. 2 +12 v input for overvoltage and undervoltage for the +12 v rail. 3 +5 v input for overvoltage and undervoltage for the +5 v rail. 4 +3.3/? v input for overvoltage and undervoltage for the +3.3 v rail or ? v rail, depending on product option. 5 ?2 v input for overvoltage and undervoltage for the ?2 v rail. this function may be disabled by tying this pin to a positive voltage above 2.4 v. 6 gnd signal ground and silicon substrate. 7 hyst open collector output of the ac undervoltage comparator. a resistor between this pin and ac will provide hysteresis to the ac undervoltage sensing. 8 off pulling this pin low will reset the fault latch and discharge the start-up timing capacitors, uvb and pg cap, allowing normal start-up for the system. pulling this pin high will send the fault signal high, prompting a system shutdown. 9 ac non-inverting input to the ac undervoltage sensing comparator. if the ac pin is less than 2.5 v, pok goes low and uvb cap discharges. 10 pg cap a cap to ground provides a delay between undervoltage sensing becoming good and the pok output going high. cap discharges whenever an output or ac undervoltage is detected. 11 pok open collector output of the undervoltage sensing comparators. this pin goes low upon an undervoltage condition. except for the delay set by the pg cap, this pin always reflects the actual state of the undervoltage sensing. 12 delay a cap to ground will delay the fault signal when the off pin is used to shut down the system. the pok will signal a power fail warning immediately, but the fault shutdown of the power supply will be delayed. 13 uvb a cap to ground provides start-up blanking of the undervoltage sensing portion of the fault signal. this pin may also be grounded to prevent undervoltage conditions from triggering the fault signal. this pin discharges the cap whenever ac goes low or fault pin goes high. 14 v ref 2.5 v voltage reference. this is a series regulator type reference. 15 fault open collector output of the overvoltage and undervoltage comparators. 16 cbd crow-bar drive output of the overvoltage faults only.
98 www.ptcc.com.tw as23xx secondary side housekeeping circuit pin function description (for as2316) pin number function description 1v cc power input to the chip. 2 +12 v input for overvoltage and undervoltage for the +12 v rail. 3 +5 v input for overvoltage and undervoltage for the +5 v rail. 4 +3.3 input for overvoltage and undervoltage for the +3.3 v rail. 5 ? v input for overvoltage and undervoltage for the ? v rail. 6 ?2 v input for overvoltage and undervoltage for the ?2 v rail. this function may be disabled by tying this pin to a positive voltage above 2.4 v. 7 gnd signal ground and silicon substrate. 8 hyst open collector output of the ac undervoltage comparator. a resistor between this pin and ac will provide hysteresis to the ac undervoltage sensing. 9 off pulling this pin low will reset the fault latch and discharge the start-up timing capacitors, uvb and pg cap, allowing normal start-up for the system. pulling this pin high will send the fault signal high, prompting a system shutdown. 10 ac non-inverting input to the ac undervoltage sensing comparator. if the ac pin is less than 2.5 v, pok goes low and uvb cap discharges. 11 pg cap a cap to ground provides a delay between undervoltage sensing becoming good and the pok output going high. cap discharges whenever an output or ac undervoltage is detected. 12 pok open collector output of the undervoltage sensing comparators. this pin goes low upon an undervoltage condition. except for the delay set by the pg cap, this pin always reflects the actual state of the undervoltage sensing. 13 delay a cap to ground will delay the fault signal when the off pin is used to shut down the system. the pok will signal a power fail warning immediately, but the fault shutdown of the power supply will be delayed. 14 uvb a cap to ground provides start-up blanking of the undervoltage sensing portion of the fault signal. this pin may also be grounded to prevent undervoltage conditions from triggering the fault signal. this pin discharges the cap whenever ac goes low or fault pin goes high. 15 v ref 2.5 v voltage reference. this is a series regulator type reference. 16 fault open collector output of the overvoltage and undervoltage comparators.
99 www.ptcc.com.tw as23xx secondary side housekeeping circuit absolute maximum ratings parameter symbol rating unit supply voltage v cc 20 v continuous power dissipation at 25? p d 1000 mw junction temperature t j 150 ? operating temperature range ? 0 to 105 ? storage temperature range t stg ?5 to 150 ? lead temperature, soldering 10 seconds t l 300 ? stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above indicated in the operational s ections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliabilit y. recommended conditions parameter symbol rating unit supply voltage v cc 5 ?12 v typical thermal resistance package ja jc typical derating 16l soic 65?/w 45?/w 10.0 mw/? 16l pdip 80?/w 35?/w 12.5 mw/? electrical characteristics electrical characteristics are guaranteed over full junction temperature range (0 to 105?). ambient temperature must be derate d based on power dissipation and package thermal characteristics. unless otherwise specified, the conditions of test are v cc = 12 v; +3.3 v = 3.3 v; +5 v = 5 v; +12 v = 12 v; ?2 v = ?2 v; ? v = ? v; off = low. parameter symbol test condition min. typ. max. unit bias supply current i cc no faults 8 12 ma min. v cc for operation v cc min. v ref = 2.5 v, no faults 4.2 v undervoltage, overvoltage +3.3 v (not available on as2350) +3.3 v undervoltage uv 2.87 2.95 3.03 v +3.3 v overvoltage ov 3.76 3.86 3.96 v +3.3 v input current i b v +3.3 = +3.3 v, v +5 = +5.0 v ?.1 0 0.1 ma +5 v +5 v undervoltage uv 4.40 4.50 4.60 v +5 v overvoltage ov 5.74 5.89 6.04 v +5 v input current i b v +5 = +5.0 v, v +3.3 = +3.3 v 1.6 2.5 ma +12 v +12 v undervoltage uv 10.25 10.50 10.60 v +12 v overvoltage ov 14.53 14.90 15.27 v +12 v input current i b v +12 = +12.0 v 0.8 1.5 ma
100 www.ptcc.com.tw as23xx secondary side housekeeping circuit electrical characteristics (cont d) electrical characteristics are guaranteed over full junction temperature range (0 to 105?). ambient temperature must be derate d based on power dissipation and package thermal characteristics. unless otherwise specified, the conditions of test are v cc = 12 v; +3.3 v = 3.3 v; +5 v = 5 v; +12 v = 12 v; ?2 v = ?2 v; ? v = ? v. parameter symbol test condition min. typ. max. unit ? v (not available on AS2333) ? v undervoltage uv ?.80 ?.00 ?.20 v ? v overvoltage ov ?.00 ?.25 ?.55 v ? v input current i b v ? = ?.0 v ?0 ?50 a ? v disable voltage v d minimum voltage to disable 2.3 2.4 v ?2 v ?2 v undervoltage uv ?.20 ?.55 ?.80 v ?2 v overvoltage ov ?4.55 ?5.04 ?5.60 v ?2 v input current i b v ?2 = ?2.0 v ?00 ?00 a ?2 v disable voltage v d minimum voltage to disable 2.0 2.2 v ac/hyst ac undervoltage uv t j = 25? 2.460 2.520 2.540 v ac input current i b ?.5 ? a hyst high state leakage i l v hyst = 5 v; ac > 2.5 v 0.01 1 a hyst output current i ol v hyst = 0.3 v; ac < 2.5 v 1 3 ma hyst low voltage v ol i hyst = 1 ma; ac < 2.5 v 0.3 v outputs pok high state leakage i l v pok = 12 v; no faults 100 200 a pok output current i ol v pok = 0.4 v; v cc = 7 v undervoltage 5 10 ma condition fault high state leakage i l v fault = 12 v; off = high 0.01 1 a fault output current v ol v fault = 0.4 v; no faults v cc = 12 v 3 10 ma v cc = 5 v 1.3 4 ma cbd (crow-bar drive) i oh overvoltage condition ?5 ?5 ma minimum output current cbd output high voltage v oh i cbd = 0 ma; t = 25 c 2.0 2.5 3.0 v i cbd = 0 ma; t = 105?; overvoltage 1.4 3.3 v condition cbd pulldown resistance r out i cbd = 1 ma; no faults 300 500 1000 1000
101 www.ptcc.com.tw as23xx secondary side housekeeping circuit electrical characteristics (cont d) electrical characteristics are guaranteed over full junction temperature range (0 to 105?). ambient temperature must be derate d based on power dissipation and package thermal characteristics. unless otherwise specified, the conditions of test are v cc = 12 v; +3.3 v = 3.3 v; +5 v = 5 v; +12 v = 12 v; ?2 v = ?2 v; ? v = ? v. parameter symbol test condition min. typ. max. unit voltage reference output voltage v ref i ref = 0 ma, t j = 25? 2.488 2.500 2.525 v line regulation ? v ref v cc = 5 v to 15 v 10 15 mv load regulation ? v ref i ref = 0 v to ? ma 10 15 mv temperature deviation* ? v ref 0 < t j < 105? 10 15 mv start-up functions uvb pull-up current source i oh v uvb = 2.0 v; no faults ?.4 ? ?.9 a uvb clamp v oh max i uvb = 10 a; no faults 2.9 3.1 3.3 v uvb discharge current i uvb v uvb = 2.0 v; fault = low; 3 8 ma (ac shutdown) ac < 2.5 v uvb discharge current i ol v uvb = 2.0 v; fault = high; 2.5 10 ma (fault shutdown) ac > 2.5 v uvb low output voltage v ol i uvb = 100 a; 0.2 v fault = low; ac < 2.5 v pg cap pull-up current source i oh v pgcap = 2.0 v; no faults ?.5 ? ?.4 a pg cap clamp v oh max i pgcap = 10 a; no faults; ac > 2.5 v 2.9 3.1 3.3 v pg cap discharge current i ol v pgcap = 2.0 v; undervoltage 2 6 ma condition pg cap low output voltage v ol i pgcap = 100 a; undervoltage 0.2 v condition off input high voltage v ih 2.0 v off input low voltage v il 0.8 v off pull-up to v cc rv off = 0 v 25 50 100 k ? delay pull-up current source i oh v delay = 0 v; off = high ?.5 ? ?.0 a delay clamp v oh max i delay = 10 a; off = high 2.9 3.1 3.3 v delay discharge current i ol v delay = 2.0 v; off = low 2.5 10 ma delay low output voltage v ol i delay = 100 a; off = low 0.2 v *temperature deviation is defined as the maximum deviation of the reference over the given temperature range and does not imply an incremental deviation at any given temperature.
102 www.ptcc.com.tw as23xx secondary side housekeeping circuit theory of operation the as23xx performs housekeeping functions for power supplies, especially switching power sup- plies for personal computers. the chip resides on the secondary side of the power supply (psu), and it performs three primary functions: 1) monitors the output voltages and reports faults 2) sequences the start-up of the psu 3) sequences the shutdown of the psu section 1 ?output voltages and faults 1.0 output voltage monitoring the as23xx monitors the standard voltage out- puts for pc type power supplies. it has inputs for +12 v, +5 v, +3.3 v, ? v and ?2 v. these inputs are tied directly to the outputs of the psu, and therefore do not require external dividers to set the error thresholds. these pins are moni- tored for both overvoltage (ov) and undervoltage (uv) conditions. the specs for these thresholds are listed in the data sheet. 1.1 overvoltage faults: fault and cbd an overvoltage condition in a power supply is considered to be a catastrophic and dangerous condition which must result in a safe, complete and near-instantaneous shutdown of the system. overvoltages most often result from a break in the system feedback and control circuitry or from a short between outputs. when the as23xx detects an overvoltage, the fault is latched inter- nally, and the fault and cbd pins go high. the fault pin is an open collector npn output which is intended to drive an optocoupler led for feed- back to the primary side controller of the psu. the cbd pin is an npn darlington output which is intended to drive an scr crowbar circuit which will short circuit the outputs of the psu. usually, just one or the other output is used depending on the psu s cost and system definition. both methods are intended to protect the customer s system, and the customer, as the first priority. 1.2 undervoltage faults: pok and fault an undervoltage condition is sometimes not con- sidered a catastrophic or dangerous condition, but always one which the customer should be warned about. the pok signal is a logic line to the customer s system that is specified in most pc type power supply systems. the as23xx will pull the pok signal low when a uv fault is detect- ed. a uv fault may or may not require the system to shut down, so an undervoltage blanking pin is provided (uvb). grounding this pin will prevent uv faults from propagating to the fault pin. cbd does not react to uv faults. 1.3 input undervoltage: ac and hyst in addition, there is a special undervoltage detec- tion input for sensing the input voltage to the power supply, designated as the ac pin. this pin will cause the pok pin to go low if there is insuf- ficient voltage to run the psu outputs. since power supplies must maintain high voltage isola- tion between the primary and secondary sides of the system, the ac pin is usually tied to a divided down and filtered representation of the second- ary side switching waveform. hysteresis for this function, to provide immunity from line ripple, is configured by the psu designer and is imple- mented with the hyst pin, which is an open col- lector output of the ac comparator. section 2 ?psu start-up sequences 2.0 system start-up sequence when the power supply starts up, the as23xx must not erroneously report a fault. in addition, most pc type power supply specifications require
103 www.ptcc.com.tw as23xx secondary side housekeeping circuit a specific timing sequence for the pok signal. some psu systems also require an isolated, low voltage, low power remote turn-on switch, rather than a large line cord switch. 2.1 vref enable of chip bias since the vcc of the as23xx comes up in a finite amount of time, and since the vref of the chip and the bias for the comparators are not within specification until approximately 4.2 v of vcc is available, the comparators for ov and uv and most other functions are disabled until vref is within spec. this prevents the false detection of a fault due to an erroneous vref. similarly, if vref is too heavily loaded and gets pulled low out of spec, these functions will also shut off. 2.2 blanking uv s during start-up: uvb as the power supply outputs come up, the under- voltage faults must be blanked to allow the supply to complete its start-up. putting a capaci- tor to ground on the uvb pin will allow the psu designer to set a specific period of time during which undervoltages will not propagate to the fault pin. the uvb pin provides a 1 a current source to charge the cap, and once the uvb pin charges above 2.5 v, the undervoltage sensing is enabled. uvb does not blank undervoltages to the pok pin. the uvb pin is clamped one diode above vref, or about 3.1 v, allowing fast dis- charge of the capacitor when the system resets. 2.3 pok bias the pok pin has some specific requirements based on industry standard pc power supply specifications. at start-up, the pok pin must not rise above 0.4 v. the pok pin is an npn open collector whose base is tied to vcc via a simple resistor. therefore, once vcc pulls above one diode or about 0.6 v, the pok pin will go low and saturate. if the pok pin external pull-up is to the 5 v output, the pok signal will not go above 0.4 v if the vcc of the as23xx is tied to the 12 v output or an auxiliary rail. 2.4 pok start-up timing: pgcap in addition to 2.3 above, most pc power supplies require the pok pin to remain low until all outputs have been good for at least 100 ms but not more than 500 ms. a cap to ground on the pgcap pin allows the psu designer to set the timing delay between the psu outputs becoming good and the pok pin going high. the pgcap pin pro- vides a 1 a current source to charge the cap, and when the cap charges above 2.5 v, the pok pin goes high. when an undervoltage occurs, the pgcap pin discharges rapidly and the pok pin goes low. the pok pin does not respond to overvoltages. 2.5 isolated remote on/off switching: off and fault a low voltage, isolated remote on/off switch may be implemented with the as23xx off pin. if the chip vcc is run off an auxiliary rail, the fault signal may be used to start and stop the psu. when the off pin is pulled from high to low or grounded, the fault pin resets to a low state, which may be used to drive an optocoupler to enable the primary side pwm controller. allowing the off pin to go open circuit or high causes the pok pin to go low immediately, and the fault pin will go high after a time delay set by a cap to ground on the delay pin. this allows the cus- tomer s system to receive a pok warning before the psu actually shuts down. section 3 ?psu shutdown sequences 3.0 shutdown sequence for normal shutdowns, the primary requirement is that the pok signal should go low some mini- mum time before the psu outputs fall out of spec.
104 www.ptcc.com.tw as23xx secondary side housekeeping circuit 3.1 delaying remote off: delay in systems which use the off and fault pins to provide remote on/off switching, the delay between the off pin going high and the fault signal going high is programmable with a capac- itor to ground on the delay pin as described in 2.5 above. the pok pin, on the other hand will go high immediately after the off pin is open cir- cuited or pulled high, giving the system warning of the impending shutdown. the delay pin pro- vides a 1 a current source to charge the cap, and when the cap charges above 2.5 v, the fault pin will go high. 3.2 ac warning prior to primary drop-out in systems where the input line voltage is switched, the ac pin threshold should be set so that it causes pok to go low before the primary bulk voltage reaches drop-out and the primary pwm shuts off. the output of the ac comparator also causes the uvb pin to pull low, so that the undervoltage sensing does not trip the fault latch as the outputs fall below spec. recall that the ac pin senses a divided down and filtered representation of the secondary side switching waveform, which will provide a proportional rep- resentation of the primary voltage via the turns ratio of the transformer.
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